Interlayered power bus for semiconductor device

ABSTRACT

A semiconductor device includes a first power pad, a second power pad, a first adjacent bus pair, and a second adjacent bus pair. The first power pad is operable to supply a first potential, and the second power pad operable to supply a second potential. The first adjacent bus pair is disposed on a first layer of the semiconductor device and connected to the first and second power pad. The second adjacent bus pair is disposed on the second layer of the semiconductor device and is connected to the first and second power pads, and is also underlying the first adjacent bus pair.

BACKGROUND

[0001] 1. Field of the Invention

[0002] The invention relates in general to semiconductor devices, andmore particularly to integrated circuit power distribution systems andmethods.

[0003] 2. Description of the Related Art

[0004] A semiconductor device, such as a semiconductor memory device,typically comprises a memory array, input/output (I/O) circuits, worddrive circuits, bit select circuits, sense amplifiers, sense amplifierdrive circuits, and other analog and digital circuits. All of thesecircuits receive power from a power distribution system in theintegrated circuit.

[0005] Data stored in the memory array is typically read by selecting amemory cell and using a sense amplifier to compare a resulting voltageor current to a reference voltage or current. Typically, the I/Ocircuits and word drive circuits are optimized for speed and may changestates rapidly. The rapid change of states often generates currenttransients or voltage transients in the power distribution system of thesemiconductor device. These resulting transients may cause performancedegradation in particular circuits, such as the bit select circuits,sense amplifiers, sense amplifier drive circuits, or other sensitiveanalog or digital circuits.

[0006] Typically, the power distribution system comprises a pair ofbusses, with one bus at a higher potential than the other bus. Dependingon the architecture of the bus pair, the conductance of the busses mayvary, which may also cause performance degradation in circuits poweredby the bus pair.

SUMMARY

[0007] A semiconductor device comprises a first power pad, a secondpower pad, and a first power network. The first power pad is operable tosupply a first potential, and the second power pad operable to supply asecond potential. The first power network comprising first busses andsecond busses interlayered on first and second layers of thesemiconductor device. The first busses are connected to the first powerpad and the second busses are connected to the second power pad.

[0008] A method of providing power to an integrated circuit comprisesthe steps of interlayering first busses on first and second layers ofthe integrated circuit, interlayering second busses on the first andsecond layers of the integrated circuit, connecting the first busses toa first potential, and connecting the second busses to a secondpotential.

[0009] A semiconductor device comprises a first power pad, a secondpower pad, a first adjacent bus pair, and a second adjacent bus pair.The first power pad is operable to supply a first potential, and thesecond power pad operable to supply a second potential. The firstadjacent bus pair is disposed on a first layer of the semiconductordevice and is connected to the first and second power pads. The secondadjacent bus pair is disposed on the second layer of the semiconductordevice and is connected to the first and second power pads. The secondadjacent bus pair is underlying the first adjacent bus pair in anelongated direction.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 is a block diagram of a semiconductor device including apower supply system;

[0011]FIG. 2 is a block diagram of an embodiment of a first and secondpower network of the power supply system;

[0012]FIGS. 3-5 are diagrams of an interlayered bus pair in the firstpower network;

[0013]FIG. 6 is a cross section view of another embodiment of theinterlayered bus pair;

[0014]FIG. 7 is a cross section view of another embodiment of theinterlayered bus pair;

[0015]FIG. 8 is a block diagram of another embodiment of the powersupply system in the semiconductor device;

[0016]FIG. 9 is a block diagram of another embodiment of the powersupply system in the semiconductor device;

[0017]FIG. 10 is a block diagram of another embodiment of the powersupply system in the semiconductor device;

[0018]FIG. 11 is a block diagram of another embodiment of the powersupply system in the semiconductor device;

[0019]FIG. 12 is a block diagram of another embodiment of the powersupply system in the semiconductor device; and

[0020]FIG. 13 is a block diagram of another embodiment of the powersupply system comprising two subsystems in the semiconductor device.

DETAILED DESCRIPTION

[0021]FIG. 1 is a block diagram of a semiconductor device 10 including apower supply system 100. The semiconductor device 10 includes a firstpower pad 102 that supplies a first potential V_(DD), and a second powerpad 104 that supplies a second potential V_(SS). The first potentialV_(DD) is typically a positive voltage relative to the second potentialV_(SS). The second potential V_(SS) is typically a ground potential or anegative voltage potential. Voltage sources may be provided fromexternal sources via a first voltage pin 112 that is connected to thefirst power pad 102 via a lead 120, and a second voltage pin 130 that isconnected to the second power pad 104 via a lead 130.

[0022] The semiconductor device 10 may comprise a semiconductor memorydevice, such as a DRAM integrated circuit, or an MRAM integratedcircuit. The semiconductor device 10 may also comprise other devices,such as processors, controllers, and the like.

[0023] The power supply system 100 illustratively comprises a firstpower network 200 that defines a first periphery 201, and a second powernetwork 300 that defines a second periphery 301 within the firstperiphery 201. The second periphery 301 may also be symmetricallydisposed from one or both of the power pads 102 and 104. Both of thefirst and second power networks 200 and 300 are connected to the firstand second power pads 102 and 104.

[0024] The first power network 200 provides power to a first pluralityof circuits on the semiconductor device 10, including input/output (I/O)circuits 402, 404, 406 and 408, and word drive circuits 410, 412, 414,and 416. The second power network 300 provides power to a secondplurality of circuits on the semiconductor device 10, including senseamplifier circuits 420, the memory array 422, and the bit selectcircuits 430 and 432.

[0025] In one embodiment, the first and second power networks comprisepairs of layered traces. FIG. 2 is a block diagram of the first andsecond power networks 200 and 300 of the power supply system 100according to this embodiment.

[0026] The first power network 200 comprises a first power bus 202connected to the first power pad 102, and a second power bus 204connected to the second power pad 104. Likewise, the second powernetwork 300 comprises a third power bus 302 connected to the first powerpad 102, and a fourth power bus 304 connected to the second power pad104. The first and third power busses 202 and 302 may coextensivelyoverlay the second and fourth power busses 204 and 304; however, forillustrative purposes, the first and third power busses 202 and 302 areslightly offset from the second and fourth power busses 204 and 304.

[0027] Typically, the semiconductor device 10 comprises multiple layers,and thus the first and second power busses 202 and 204 and the third andfourth power busses 302 and 304 may be separated by one or more layers.In another embodiment, however, the first and second power busses 202and 204 and the third and fourth power busses 302 and 304 may bedisposed on the same layer and separated by an insulating material.

[0028] The power busses 202, 204, 302 and 304 are typically formed froma low resistance conductor, such as aluminum, copper, gold, or otherconductive metal or material, and deposited in a loop manner as shown todefine the peripheries 201 and 301. Word drive circuits 410, 412, 414and 416 are connected to the first and second power busses 202 and 204,and the bit selection circuits 430 and 432 are connected to the thirdand fourth power busses 302 and 304. Illustratively, the word drivecircuit 410 is connected to the first power bus 202 by lead 440, and tothe second power bus 204 by lead 441. The remaining word drive circuits412, 414, and 416 are connected to the first and second power busses 202and 204 by leads 442, 443, 444, 445, 446, and 447 in a similar manner.The bit selection circuit 430 is connected to the third power bus 302 bya lead 448 and to the fourth power bus 304 by a lead 449; likewise, thebit selection circuit 432 is connected to the third and fourth powerbusses 302 and 304 by the leads 450 and 451 in a similar manner.

[0029] The I/O circuits 402, 404, 406 and 408, the sense amplifiercircuits 420, and the memory array 422 are connected to the first andsecond power networks 100 and 200 in a similar manner, but are notdepicted in FIG. 2 so as to avoid congestion in the drawings.

[0030] In operation, the I/O circuits 402, 404, 406 and 408, and theword drive circuits 410, 412, 414, and 416 may change states rapidly,which in turn may cause voltage or current transients in the first powernetwork 200. For example, a state change in the word drive circuit 414may cause a voltage transient of several millivolts at the node definedby the first power bus 202 and the lead 442. The transient or noise onthe power system 200 caused by the I/O circuits 402, 404, 406 and 408,and word drive circuits 410, 412, 414, and 416 may be of such magnitudeto cause performance degradation in more sensitive circuits, such as thesense amplifier circuits 420, the memory array 422, and the bit selectcircuits 430 and 432.

[0031] The power system 100 of FIG. 1 reduces or eliminates the effectsof such noise. As the transient propagates over the first power bus 202and back to the first power pad 102, the magnitude of the transientattenuates due to the inherent bus impedance.

[0032] Upon reaching the first power pad 102, the transient may beclamped to V_(DD) at the first power pad 102. Accordingly, the transientis prevented from propagating over the second power network 300 andaffecting the performance of the sense amplifier circuits 420, thememory array 422, and the bit select circuits 430 and 432. If thetransient is of a sufficient magnitude, however, then the voltage at thefirst power pad 102 may be temporarily affected by the transient. Whenthis occurs, the transient is symmetrically distributed over the secondpower network 300. Because the circuits connected to the second powernetwork 300 are referenced from the first power pad 102, the transientis superimposed on the third power bus 302 and distributed equally toall circuits connected to the third power bus 302. The equaldistribution over the third power bus 302 results in common voltagevariations among the sense amplifier circuits 420, the memory array 422,and the bit select circuits 430 and 432, and thus minimizes oreliminates performance degradation that may result from a voltageimbalance or voltage transient on the third power bus 302.

[0033] In a similar manner, voltage or current transients induced on thesecond power bus 204 in the first power network 200 are likewiseprevented from propagating over the second power network 300 by beingclamped at the second power pad 104, or performance degradation in thesense amplifier circuits 420, the memory array 422, and the bit selectcircuits 430 and 432 is minimized or eliminated by the commondistribution of the transient through the fourth power bus 304.

[0034] Thus, circuits with a higher tolerance to power bus noise, ornoise inducing circuits, may be powered by the first power network 200,and noise sensitive circuits may be powered by the second power network300. Accordingly, performance degradation in the noise sensitivecircuits may be minimized or even eliminated.

[0035] Another source of performance degradation for circuits connectedto a power system may be caused by conductance variations in a bustrace, or by conductance variations between a pair of bus traces, suchas power busses 202 and 204. Typically, conductance variations arecaused by nonuniform bus traces, bus trace thickness, or by dividing abus pair between one or more layers in the semiconductor device. Othersources of conductance variations in the bus traces may also causeperformance degradation in circuits connected to the bus traces.

[0036]FIGS. 3-5 are block diagrams of an interlayered bus pair in thefirst power network 200. The power network 200 of FIGS. 3-5 minimizesconductance variations in a power bus. In the embodiment of FIGS. 3-5,the first power network 200 comprises first and second interlayeredbusses. The first interlayered bus comprises first and second subbusses210 and 212 interlayered on first and second layers 502 and 504 of thesemiconductor device 10. Similarly, the second interlayered buscomprises third and fourth subbusses 220 and 222 interlayered on firstand second layers 502 and 504 of the semiconductor device 10.

[0037] The first and second subbusses 210 and 212 are connected to thefirst power pad 102 and thus are at the potential V_(DD), and the thirdand fourth subbusses 220 and 222 are connected to the second power pad104 and thus are at the potential V_(SS). The first and third subbusses210 and 220 may be juxtaposed on the first layer 502 of thesemiconductor device 10, and the second and fourth subbusses 212 and 222may be juxtaposed on the second layer 504 of the semiconductor device10.

[0038] As shown in FIGS. 3 and 4, the width of the third and fourthsubbusses 220 and 222 may extend in an overlying relationship at one ormore locations in the power network 200 so that the third subbus 220 maybe connected to the fourth subbus 222 through the first and secondlayers 502 and 504 of the semiconductor device 10. Likewise, as shown inFIGS. 3 and 5, the width of the first and second subbusses 210 and 212may extend in an overlying relationship at one or more locations in thepower network 200 so that the second subbus 210 may be connected to thethird subbus 212 through the first and second layers 502 and 504 of thesemiconductor device 10. These extensions may alternate and the firstand fourth subbusses 210 and 222 and the second and third subbusses 212and 220 may thus be connected at multiple locations, as indicated by thecross sections AA′ and BB′ of FIG. 3.

[0039] These connections minimize or eliminate the conductancevariations caused by nonuniform bus traces, bus trace thickness, or bydividing the bus pair between one or more layers in the semiconductordevice 10. Thus, by vertically splitting the busses 202 and 204 of FIG.1 in the manner as shown in FIG. 3, the total conductance of each splitbus is equalized.

[0040]FIG. 6 is a cross section view of another embodiment of theinterlayered bus pair in the power network 200. In this embodiment, thewidth of the busses 210, 212, 220, and 222 is uniform, and the busses210 and 220 overlap the busses 222 and 212 coextensively. The connectionof the first and second subbusses 210 and 212 is facilitated by a crossconnection between the first and second layers 502 and 504 at a firstlocation. Likewise, the connection of the third and fourth subbusses 220and 222 is facilitated by a cross connection between the first andsecond layers 502 and 504 at a second location. The cross connectionsmay alternate and be evenly distributed along the subbusses 210, 212,220 and 222.

[0041]FIG. 7 is a cross section view of another embodiment of theinterlayered bus pair in the power network 200. In this embodiment, thefirst and second subbusses 210 and 212 are vertically disposed on thefirst and second layers 502 and 504 so that the first subbus 210 tocoextensively overlaps the second subbus 212. Likewise, the third andfourth subbusses 220 and 222 are vertically disposed on the first andsecond layers 502 and 504 so that the third subbus 220 coextensivelyoverlaps the fourth subbus 222. The vertical and horizontal dispositionof the subbusses 210, 212, 220, and 222 of FIG. 7 provide for reducedline-to-line capacitance as compared to the vertical and horizontaldisposition of the subbusses 210, 212, 220, and 222 of FIGS. 4-6. Thus,depending on the particular requirements of semiconductor device 10, theline-to-line capacitance of the power system 200 may be increased ordecreased by selecting the vertical and horizontal disposition of thesubbusses 210, 212, 220 and 222.

[0042] The first power network 200 of FIGS. 3-6 may be utilized as themain power network for a semiconductor device and thus provide power toall circuits in the semiconductor device. In another embodiment,however, the first power network 200 of FIGS. 3-6 may be combined withthe second power network 300 of FIGS. 1 and 2 to minimize or eliminateperformance degradation in circuits connected to the second powernetwork 300 that may result from a voltage imbalance or other transientinduced on the first power network 200. Furthermore, the second powernetwork 300 of FIGS. 1 and 2 may also be realized by the interlayeredadjacent bus pair as described with reference to FIGS. 3-6. Thus, thesecond power network 300 may comprise fifth, sixth, seventh and eightsubbusses arranged in manner similar to the first, second, third andfourth subbusses 210, 212, 220, and 222 of the first power network 200.

[0043] While the first power network 200 of FIGS. 3-7 has been describedas being distributed over two layers, the first power network may bedistribute over additional layers. For example, the first and secondsubbusses 210 and 212 may be disposed on first and second layers,respectively, and the third and fourth subbusses 220 and 222 may bedisposed on first and third layers, respectively. In another embodiment,the first and fourth subbusses 210 and 222 may be disposed on first andsecond layers, respectively, and the second and third subbusses 212 and220 may be disposed on first and third layers, respectively. And in yetanother embodiment, multiple subbusses may be disposed in multiplelayers, e.g., six subbusses may be disposed over three layers, or twelvesubbusses may be disposed over six layers.

[0044] While the geometry of the first and second peripheries 201 and301 of FIGS. 1 and 3 are rectangular, other geometric patterns may alsobe used. FIG. 8 is a block diagram of another embodiment of the powersupply system 100 in the semiconductor device 10. In this embodiment,the geometry of the first periphery 201 is rectangular, and the geometryof the second periphery 301 is circular. Other geometric patterns forthe first and second peripheries 201 and 301 may also be used.

[0045] Furthermore, the first and second power pads 102 and 104 need notbe placed between the first and second power networks 200 and 300 asdepicted in FIG. 1. For example, in the embodiment of FIG. 8, the firstand second power pads 102 and 104 are located outside of the peripheries201 and 302 defined by the first and second power networks 200 and 300,respectively. In all other respects, the first and second power networks200 and 300 may be constructed and may operate in a similar manner asdescribed with reference to FIGS. 1-7.

[0046] The first and second power pads 102 and 104 may also be placed atother locations on the semiconductor device 10. FIG. 9 is a blockdiagram of another embodiment of the power supply system 100 in thesemiconductor device 10. In this embodiment, the first power pad 102 ispositioned in the upper left quadrant of the rectangle area defined bythe first periphery 201 of the first power network 200, and the secondpower pad 104 is positioned in the lower right quadrant of the areadefined by the first periphery 201. In all other respects, the first andsecond power networks 200 and 300 may be constructed and may operate ina similar manner as described with reference to FIGS. 1-8.

[0047] Typically, circuits that induce noise on a power system, orcircuits that have a relatively high noise tolerance, will be connectedto the first power network 200. Accordingly, the first power network 200can be asymmetrically disposed from the first and second power pads 102and 104, as depicted in FIG. 10, which is a block diagram of anotherembodiment of the power supply system 100 in the semiconductor device10. In this embodiment, the second power network 300 is symmetricallydisposed between the first and second power pads 102 and 104 by theaddition of traces 320 and 322. One or both of the first power network200 and the second power network 300 may comprise overlapping busses asdescribed with reference to FIGS. 1 and 2, or interlayered busses asdescribed with reference to FIGS. 3-6. In all other respects, the firstand second power networks 200 and 300 may be constructed and may operatein a similar manner as described with reference to FIGS. 1-9.

[0048] Additionally, more than one pair of first and second power pads102 and 104 may be provided on the semiconductor device 10. FIG. 11 is ablock diagram of another embodiment of the power supply system 100 inthe semiconductor device 10. In this embodiment, the first power pad 102is connected to the first voltage pin 112 via a connection 120, and thesecond power pad 104 is connected to the second voltage pin 114 via aconnection 130. The first and second power pads 102 and 104 providepotentials V_(DD) and V_(SS), respectively, to the first power network200.

[0049] A third power pad 106 is also connected to the first pin 112 viaa connection 122, and a fourth power pad 108 is also connected to thesecond pin 114 via a connection 132. The third and fourth power pads 106and 108 provide potentials V_(DD) and V_(SS), respectively, to thesecond power network 300. In this embodiment, transients induced in thefirst power network 200 on the V_(DD) bus must propagate back to thefirst power pad 102, and through the connections 120 and 122 beforereaching the third power pad 106. Accordingly, the transients undergofurther attenuation due to the inherent impedance of the connections 120and 122, and may also be clamped by the first pin 112. Likewise,transients induced in the first power network 200 on the V_(SS) bus mustpropagate back to the second power pad 104, and through the connections130 and 132 before reaching the fourth power pad 108. Accordingly, thetransients undergo further attenuation due to the inherent impedance ofthe connections 130 and 132, and may also be clamped by the second pin114. In all other respects, the first and second power networks 200 and300 may be constructed and may operate in a similar manner as describedwith reference to FIGS. 1-10.

[0050] The embodiments of FIGS. 1-11 have depicted looped bus tracesdefining first and second peripheries 201 and 301. However, other bustraces may also be used. FIG. 12 is a block diagram of anotherembodiment of the power supply system 100 in the semiconductor device10. In this embodiment, the first power network 200 comprises a firstouter bus extension 230 disposed on a first side of the semiconductordevice 10 and a second outer bus extension 232 disposed on a second sideof the semiconductor device 10. The first and second outer busextensions 230 and 232 are connected to the first power pad 102.

[0051] Likewise, the first power network 200 also comprises a thirdouter bus extension 234 disposed on the first side of the semiconductordevice 10 and a fourth outer bus extension 236 disposed on the secondside of the semiconductor device 10. The third and fourth outer busextensions 234 and 236 are connected to the second power pad 104. Thefirst and third outer bus extensions 230 and 234 overlap to define afirst outer overlay region 240, and the second and third outer busextensions 232 and 236 overlay to define a second outer overlay region242. Power is provided to circuits connected to the first power network100, such as word line driver circuits 410 and 414, at or near the firstand second outer overlay regions 240 and 242.

[0052] Similarly, the second power network 300 comprises a first innerbus extension 330 disposed on the first side of the semiconductor device10 and a second inner bus extension 332 disposed on the second side ofthe semiconductor device 10. The first and second inner bus extensions330 and 332 are connected to the first power pad 102. A third inner busextension 334 is disposed on the first side of the semiconductor device10 and a fourth inner bus extension 336 is disposed on the second sideof the semiconductor device 10. The third and fourth inner busextensions 334 and 336 are connected to the second power pad 104. Thefirst and third inner bus extensions 330 and 334 overlap to define afirst inner overlay region 340, and the second and third inner busextensions 332 and 336 overlay to define a second inner overlay region342. Power is provided to circuits connected to the second power network300, such as the sense amplifier circuits 420, and the memory array 422at or near the first and second inner overlay regions 340 and 342.

[0053] Additionally, within the first outer overlay region 240, thefirst outer bus extension 230 and the third outer bus extension 234 maycomprise an interlayered bus structure as depicted in FIGS. 3-7.Likewise, within the second outer overlay region 242, the second outerbus extension 232 and the fourth outer bus extension 236 may comprisethe interlayered bus structure as depicted in FIGS. 3-7. The first andsecond inner overlay regions 340 and 342 may also be constructed tocomprise interlayered bus structure as depicted in FIGS. 3-7. In allother respects, the first and second power networks 200 and 300 may beconstructed and may operate in a similar manner as described withreference to FIGS. 1-11.

[0054] More than one pair of first and second power networks 200 and 300may be provided on a semiconductor device 10. FIG. 13 is a block diagramof another embodiment of the power supply system comprising twosubsystems 100 a and 100 b in the semiconductor device 10. In thisembodiment, a first power supply subsystem 100 a provides power to afirst section of the semiconductor device 10, and a second power supplysubsystem 100 b provides power to a second section of the semiconductordevice 10.

[0055] Additionally, the embodiment of FIG. 13 also illustrates analternate positioning of the first and second power pads 102 and 104. Inthis embodiment, the first and second power pads 102 and 104 areadjacent. The second power network 300 may be symmetrically disposedwith respect to the first and second power pads 102 and 104 via busleads 360 and 362. In all other respects, the first and second powernetworks 200 and 300 may be constructed and may operate in a similarmanner as described with reference to FIGS. 1-12.

[0056] Of course, variations of the embodiments described herein exist.For example, depending on the architecture of the semiconductor device10, noise inducing circuits can be powered by the second power network300, and more sensitive circuits can be powered by the first powernetwork 200. The interlayered bus of FIGS. 3-7 may also be extended to aplurality of layers in a multi-layered semiconductor device 10.

[0057] In another embodiment, only one of the third and fourth powerbusses 302 and 304 may be symmetrically disposed from the power pads 102and 104. For example, if the first power bus 202 is noisy, but thesecond power bus 204 is relatively stable, then only the third power bus302 may be symmetrically disposed from the first power pad 102.

[0058] In yet another embodiment, the first and second power networks200 and 300 may define exclusive peripheries, i.e., neither the first orsecond power networks 200 and 300 are located within the periphery ofthe other. This particular embodiment may be implemented to accommodatea semiconductor device architecture in which circuits with a highertolerance to power bus noise, or noise inducing circuits, are located ona first half of the semiconductor device, and noise sensitive circuitsare located on a second half of the semiconductor device. Accordingly,the first power network 200 may provide power to the first half of thesemiconductor device 10, and the second power network may provide powerto the second half of the semiconductor device 10.

[0059] Finally, this written description uses examples to disclose theinvention, including the best mode, and also to enable a person skilledin the art to make and use the invention. The patentable scope of theinvention is defined by the claims, and may include other examples thatoccur to those skilled in the art. Such other examples are intended tobe within the scope of the claims if they have elements that do notdiffer from the literal language of the claims, or if they includeequivalent elements with insubstantial differences from the literallanguage of the claims.

What is claimed is:
 1. A semiconductor device, comprising: a first powerpad operable to supply a first potential; a second power pad operable tosupply a second potential; and a first power network comprising firstbusses and second busses interlayered on first and second layers of thesemiconductor device, the first busses connected to the first power padand the second busses connected to the second power pad.
 2. Thesemiconductor device of claim 1, wherein: the first busses comprisefirst and second subbusses connected to the first power pad, the firstsubbus disposed on the first layer of the semiconductor device, and thesecond subbus disposed on the second layer of the semiconductor device;and the second buses comprise third and fourth subbusses connected tothe second power pad, the third subbus disposed on the first layer ofthe semiconductor device and the fourth subbus disposed on the secondlayer of the semiconductor device; wherein the first and third subbussesare juxtaposed on the first layer of the semiconductor device and thesecond and fourth subbusses are juxtaposed on the second layer of thesemiconductor device.
 3. The semiconductor device of claim 2, wherein:the first and second subbusses are connected through the first andsecond layers of the semiconductor device; and the third and fourthsubbusses are connected through the first and second layers of thesemiconductor device.
 4. The semiconductor device of claim 3, wherein:the first subbus is overlying the fourth subbus in a lengthwisedirection; and the second subbus is overlying the third subbus in alengthwise direction.
 5. The semiconductor device of claim 3, wherein:the first subbus is overlying the second subbus in a lengthwisedirection; and the third subbus is overlying the fourth subbus in alengthwise direction.
 6. The semiconductor device of claim 1, whereinthe first and second busses define a first periphery, and furthercomprising: a second power network comprising third and fourth bussesinterlayered on the first and second layers of the semiconductor device,the third buses connected to the first power pad and the fourth busesconnected to the second power pad, and wherein the third and fourthbusses define a second periphery disposed within the first periphery. 7.The semiconductor device of claim 6, wherein: the first bus comprisesfirst and second subbusses connected to the first power pad, the firstsubbus disposed on the first layer of the semiconductor device and thesecond subbus disposed on the second layer of the semiconductor device;and the second bus comprises third and fourth subbusses connected to thesecond power pad, the third subbus disposed on the first layer of thesemiconductor device and the fourth subbus disposed on the second layerof the semiconductor device.
 8. The semiconductor device of claim 7,wherein: the third bus comprises fifth and sixth subbusses connected tothe first power pad, the fifth subbus disposed on the first layer of thesemiconductor device and the sixth subbus disposed on the second layerof the semiconductor device; and the fourth bus comprises seventh andeighth subbusses connected to the second power pad, the seventh subbusdisposed on the first layer of the semiconductor device and the eighthsubbus disposed on the second layer of the semiconductor device.
 9. Thesemiconductor device of claim 8, wherein: the first and second subbussesare connected through the first and second layers; the third and fourthsubbusses are connected through the first and second layers; the fifthand sixth subbusses are connected through the first and second layers;and the seventh and eighth subbusses are connected through the first andsecond layers.
 10. The semiconductor device of claim 6, wherein thesecond periphery is symmetrically disposed between the first power padand the second power pad.
 11. The semiconductor device of claim 10,wherein the first periphery is symmetrically disposed between the firstpower pad and the second power pad.
 12. The semiconductor device ofclaim 11, wherein the first and second peripheries are defined by acommon geometry.
 13. The semiconductor device of claim 10, wherein thesemiconductor device is a magnetoresistive random access memory (MRAM)device.
 14. The semiconductor device of claim 13, further comprising: amemory array comprising magnetoresistive storage elements; word linecircuitry coupled to the memory array and the first power network; andsense amplifier circuitry coupled to the memory array and the secondpower network.
 15. The semiconductor device of claim 1, wherein thefirst and second busses comprise bus extensions extending from the firstand second power pads and define overlay regions.
 16. The semiconductordevice of claim 1, wherein the semiconductor device is amagnetoresistive random access memory (MRAM) device.
 17. Thesemiconductor device of claim 16, wherein the first buses comprisesfirst and second subbusses connected to the first power pad, the firstsubbus disposed on the first layer of the semiconductor device, and thesecond subbus disposed on the second layer of the semiconductor device.18. The semiconductor device of claim 17, wherein the second busescomprises third and fourth subbusses connected to the second power pad,the third subbus disposed on the first layer of the semiconductor deviceand the fourth subbus disposed on the second layer of the semiconductordevice.
 19. The semiconductor device of claim 18, wherein the first andthird subbusses are juxtaposed on the first layer of the semiconductordevice and the second and fourth subbusses are juxtaposed on the secondlayer of the semiconductor device.
 20. The semiconductor device of claim18, wherein: the second and fourth subbusses define a lower concentricloop, and the first and third subbusses define an upper concentric loop,the upper concentric loop overlying the lower concentric loop.
 21. Amethod of providing power to an integrated circuit, the methodcomprising: interlayering first busses on first and second layers of theintegrated circuit; interlayering second busses on the first and secondlayers of the integrated circuit; connecting the first busses to a firstpotential; connecting the second busses to a second potential.
 22. Themethod of claim 21, further comprising the steps of: placing one of thefirst busses and one of the second busses in juxtaposition on the firstlayer; and placing one of the first busses and one of the second bussesin juxtaposition on the second layer.
 23. The method of claim 22,wherein the steps of interlayering first busses and interlayering secondbusses comprises the steps of: defining a first periphery, and providingthe interlayered busses along the first periphery.
 24. The method ofclaim 21, further comprising the steps of: interlayering third busses onthe first and second layers of the integrated circuit; interlayeringfourth busses on the first and second layers of the integrated circuit;connecting the third busses to the first potential; and connecting thefourth busses to the second potential.
 25. The method of claim 24,further comprising the steps of: placing one of the first busses and oneof the second busses in juxtaposition on the first layer; placing one ofthe first busses and one of the second busses in juxtaposition on thesecond layer; placing one of the third busses and one of the fourthbusses in juxtaposition on the first layer; and placing one of the thirdbusses and one of the fourth busses in juxtaposition on the secondlayer.
 26. The method of claim 25, wherein: the steps of interlayeringfirst busses and interlayering second busses comprises the steps of:defining a first periphery; and providing the interlayered first andsecond busses along the first periphery; and the steps of interlayeringthe third busses and interlayering fourth busses comprises the steps of:defining a second periphery; and providing the third and fourthinterlayered busses along the second periphery.
 27. The method of claim26, wherein the steps of defining a second periphery comprises the stepsof symmetrically disposing the second periphery between the first andsecond potentials.
 28. The method of claim 27, wherein the step ofdefining a first periphery comprises the step of symmetrically disposingthe first periphery between the first and second potentials.
 29. Themethod of claim 28, wherein the first and second peripheries are definedby a common geometry.
 30. The method of claim 21, wherein the step ofinterlayering first busses on first and second layers of the integratedcircuit comprises the steps of: depositing a first upper bus trace onthe first layer; and depositing a first lower bus trace on the secondlayer.
 31. The method of claim 30, wherein the step of interlayeringsecond busses on the first and second layers of the integrated circuitcomprises the steps of: depositing a second upper bus trace on the firstlayer; and depositing a second lower bus trace on the second layer. 32.The method of claim 31, further comprising the step of overlying thesecond lower bus trace in a lengthwise direction with the first upperbus trace.
 33. The method of claim 32, further comprising the step ofoverlying the first lower bus trace in a lengthwise direction with thesecond upper bus trace.
 34. The method of claim 31, further comprisingthe steps of: forming an upper adjacent trace pair with the first upperbus trace and the second upper bus trace; and forming a lower adjacenttrace pair with the first lower bus trace and the second lower bustrace.
 35. The method of claim 34, further comprising the step ofoverlying the lower adjacent trace pair with the upper adjacent tracepair.
 36. A system for providing power to an integrated circuit,comprising: first interlayered bus means for providing first busses onfirst and second layers of the integrated circuit; second interlayeredbus means for providing second busses on the first and second layers ofthe integrated circuit; means for connecting the first busses to a firstpotential; and means for connecting the second busses to a secondpotential.
 37. The system of claim 36, wherein: one of the first bussesand one of the second busses are in juxtaposition on the first layer;and one of the first busses and one of the second busses are injuxtaposition on the second layer.
 38. The system of claim 37, whereinthe first and second interlayered bus means define a first periphery.39. The system of claim 36, further comprising: third interlayered busmeans for providing third busses on the first and second layers of theintegrated circuit; fourth interlayered bus means for providing fourthbusses on the first and second layers of the integrated circuit; meansfor connecting the third busses to the first potential; and means forconnecting the fourth busses to the second potential.
 40. The system ofclaim 39, wherein: one of the first busses and one of the second bussesin juxtaposition on the first layer; one of the first busses and one ofthe second busses in juxtaposition on the second layer; one of the thirdbusses and one of the fourth busses in juxtaposition on the first layer;and one of the third busses and one of the fourth busses injuxtaposition on the second layer.
 41. The system of claim 40, wherein:the first and second interlayered bus means define a first periphery;and the third and fourth interlayered bus means define a secondperiphery, the second periphery within the first periphery.
 42. Thesystem of claim 41, wherein the second periphery is symmetricallydisposed between the means for connecting the third busses to a firstpotential and the means for connecting the fourth busses to a secondpotential.
 43. The system of claim 42, wherein the first periphery issymmetrically disposed between the means for connecting the first bussesto a first potential and the means for connecting the second busses to asecond potential.
 44. The method of claim 43, wherein the first andsecond peripheries are defined by a common geometry.
 45. A semiconductordevice, comprising: a first power pad operable to supply a firstpotential; a second power pad operable to supply a second potential; anda first adjacent bus pair disposed on a first layer of the semiconductordevice, the first adjacent bus pair connected to the first and secondpower pads; and a second adjacent bus pair disposed on the second layerof the semiconductor device, the second adjacent bus pair connected tothe first and second power pads and underlying the first adjacent buspair in an elongated direction.
 46. The semiconductor device of claim45, wherein: the first adjacent bus pair comprises a first bus connectedto the first power pad and a second bus connected to the second powerpad; and the second adjacent bus pair comprises a third bus connected tothe first power pad and a fourth bus connected to the second power pad.47. The semiconductor device of claim 46, wherein the first bus isoverlying the third bus.
 48. The semiconductor device of claim 46,wherein the first bus is overlying the fourth bus.
 49. The semiconductordevice of claim 45, wherein: the first adjacent bus pair defines a firstgeometry; and the second adjacent bus pair defines a second geometry,the second geometry underlying the first geometry.
 50. The semiconductordevice of claim 49, wherein the first geometry and second geometry arerectangular.
 51. The semiconductor device of claim 49, wherein the firstgeometry and second geometry are circular.
 52. The semiconductor deviceof claim 45, wherein the first and second adjacent bus pairs comprisebus extensions extending from the first and second power pads and defineoverlay regions.
 53. A semiconductor device, comprising: a first powerpad operable to supply a first potential; a second power pad operable tosupply a second potential; and a first power network comprising firstbusses and second busses interlayered on a plurality of layers of thesemiconductor device, the first busses connected to the first power padand the second busses connected to the second power pad.
 54. Thesemiconductor device of claim 53, wherein the first busses are connectedthrough each of the plurality of layers, and second busses are connectedthrough each of the plurality of layers.
 55. The semiconductor device ofclaim 53, wherein the first busses are adjacent to the second busses oneach of the plurality of layers.